1. Field of the Invention
The present invention relates generally to SRAMs on board an ASIC. More particularly, it relates to such SRAMs that may be dynamically used as a cache memory, and a cache controller therefore. The present invention may be especially suitable for use with an embedded processor such as those commonly used is printers, all-in-one units, or other devices that perform operations on image data.
2. Description of the Related Art
Multifunctional devices such as a printer/scanner/copier, other all-in-one devices, or the like, are commonplace. As is known to those skilled in the art, such devices generally have a scanner bar which either moves relative to an original document, or is stationary as the original document passes by. These devices also have a printing assembly for forming an image on a substrate, mechanical devices to feed the substrate, original documents, scanner bar, ink supply and the like.
Typically, such multifunction devices have a printed circuit board (PCB) carrying a number of components to control various operations. FIG. 1 shows a layout of a typical PCB 100 of the sort used in such a device. It is understood that the wiring, bus lines, etc. have been omitted from this figure. The PCB 100 carries a number of components, and some of the more important of these are briefly discussed.
First and foremost, the PCB 100 carries an application specific integrated circuit (ASIC) 102 which provides the majority of the control (both in hardware and firmware) for the multifunctional device. The controller ASIC 102 typically contains mostly digital logic. It is understood that the controller ASIC 102 may be a single chip, as shown in FIG. 1, or may be implemented as a chip set.
The controller ASIC 102 communicates with a number of other components resident on the PCB. These include a volatile system memory 104, a non-volatile memory 106, an analog ASIC 108, motor driver circuitry 110, analog front end 112, communication devices 114, sensors 116 and connectors 118. It is understood that there may be one or more of each of these, as needed.
The volatile system memory 104 is used to store and retrieve processor instructions and data. This memory is also used by any custom hardware assistance to store data such as image data. The non-volatile memory 106 (SFLASH, NVRAM, etc.) is used to store the firmware base (compiled microprocessor code plus any extra data needed to run the device) so that on power-up, processor code can be transferred from the slow non-volatile memory to 106 the fast volatile system memory 104. From the fast volatile system memory, the processor will execute its code base.
The analog ASIC 108 typically contains the analog circuitry necessary to deliver the appropriate voltage levels to the components on the PCB 100 (e.g. 5V, 3.3V, 1.8V). This ASIC 108 may also contain motor drivers and other analog electronics needed by the device.
The motor driver circuitry 110, which may be implemented as one or more special ASICs or comprised of discrete components (e.g. transistors, resistors, etc), converts digital control signals to speed and position control signals for the motors of the multifunction device.
The analog front end 112 (AFE) is used to convert the analog signals from the scanner bar to digital signals for use in the controller ASIC. This chip provides image data from a scanner to the controller ASIC.
The miscellaneous communication devices 114 may provide a means of communication to and from other devices such as a personal computer (PC), card readers, digital cameras, etc. These devices may simply be connectors or may contain discrete components such as ASICs and other components.
The sensors 116 may be present to detect things such as open covers, media position, and the like.
The connectors 118 are present to connect the PCB to other pieces of the device such as the motors, op-panel, scanner bar, printheads, etc.
Other components not shown such as resistors, capacitors, inductors, voltage regulators, etc. are typically located on the PCB 100 and serve a variety of functions to complete the electronics for the PCB 100.
The controller ASIC 102 for a multifunction device is charged with a number of tasks. Included among these are image processing operations, such as for rendering an image line by line. To increase performance for such memory-intensive tasks, the ASIC 102 may be provided with a sizable onboard static random access memory (SRAM) and may also be provided with a cache memory for quick access to instructions and/or data that otherwise may reside in volatile memory 104.
Generally speaking, a cache is a memory that is typically only accessible by the processor and is used to store a certain number of recently accessed data words. The number of data words that may be stored is determined by the size of the cache memory. A cache may improve processor throughput by allowing the processor to retrieve data without waiting for the typically longer access latency of the main memory. Also, main memory may be shared by other system functions, such as a Direct Memory Access (DMA) controller, and the cache allows the processor to retrieve data without waiting for another function to relinquish control of main memory.
A cache is typically divided into multiple word segments with a base address maintained for each section by the control logic. The amount of control logic needed to store the base addresses increases as the number of sections increases. The cache control logic compares the address of an incoming memory request to the stored base addresses and a match is considered a cache hit, while no match is considered a cache miss. In the event of a cache hit, the cache advantage is realized because the cache controller recognizes the address as one from a previous access and can retrieve the requested information from the cache memory quickly. In the event of a cache miss, the cache controller replaces a section of the cache memory with a new section of data from main memory. The most common replacement schemes utilized by cache controllers are replacement of the least recently used or the least frequently used section. Ideally, cache hits will occur multiple times for the same addresses and the cache will provide a performance advantage, as compared to a system that uses no cache.
In an ASIC having an internal processor, a cache may be implemented with fast access memories such as Synchronous Random Access Memories (SRAMs). The cache memory is typically bundled with and only accessible by the processor for the sole purpose of caching instructions or data. Larger cache memories typically translate to increased performance at the cost of increased die area and increased ASIC price.
FIG. 2 shows a number of components belonging to conventional controller ASIC 202 for a multifunction device. The dashed 203 line separates the controller ASIC 202 from the remainder of the PCB 100 and the solid lines between the various components illustrate information flow, rather than discrete physical connections. The dotted line 230 denotes control and other signaling from a processor 206 to the other circuitry. This control may be implemented by Advanced Microprocessor Bus Architecture (AMBA) protocols. The conventional controller ASIC 202 includes the processor 206, a cache controller 208 and a dedicated cache SRAM 210. Upon receiving an address from the processor, the cache controller 208 determines whether the dedicated cache 210 has the required information. If there is a cache hit, the requested information is retrieved from the dedicated cache 210; if not, the cache controller retrieves the requested information from main memory 204, along with adjacent information in accordance with the cache protocol.
The conventional controller ASIC 202 also includes a plurality of image processing modules 222-1, 222-N which perform specific tasks and directly communicate with the processor 206. Each of these modules 222-1, 224-N has an associated task-specific SRAM 212-1, 212-N, respectively. In general, these task-specific SRAMs 212-1, 212-N are physically located adjacent to their respective modules 222-1, 222-N and are not contiguous with one another, or with other memory on the ASIC, such as the dedicated cache memory 210. Furthermore, it is understood that while only two such modules and SRAMs are shown, that there may instead be other numbers of these, such as 1, 3, 4, or even more. As seen in the prior art embodiment of FIG. 2, the image processing modules 222-1, 222-N are the only entities that may read to or write from the task-specific SRAMs 212-1, 212-N, respectively. Significantly, the cache controller 208 of the conventional controller ASIC 202, which has a dedicated cache 210, does not directly write to or read from the task-specific SRAMs 212-1, 212-N as cache memories.
Prior art systems having memories that can be reconfigured are known in the art. An example of such as memory can be found in U.S. Pat. No. 6,678,790, whose contents are incorporated by reference.